In order to retrieve information from a magnetic memory array, a sense amplifier typically compares the current flowing through a memory cell under an applied voltage to a reference current. The reference current is generated by applying voltage to a set of reference cells, half of which are set to the high conductance state (“0” or P) and the other half to the low conductance state (“1” or AP), where “P” signifies that the magnetic domains of the cell are oriented in the same direction and “AP” signifies that the magnetic domains of the cell are oriented in opposite directions. The average current from the reference cells is then compared to the current from the memory cell, and a logical “0” or “1” output is generated by the sense amplifier. A schematic of an example of such an array is shown in FIG. 1, wherein each sense amplifier 10 is connected to at least one set of reference bit lines, RBL1 and RBL2, through a biasing and averaging circuitry 11, and connected to a set of memory cells 13 through biasing and selection circuitry 12. Generally each reference bit line is connected to several reference devices 14 and 15. For illustration, two reference devices 14 and 15 are shown for each bit line in FIG. 1. Reference word lines RWL1 and RWL2 select the reference device to be used. Similarly memory word lines WL1 and WL2 select the device to be read. In the simple implementation each memory word line WL1 and WL2 has its own set of reference cells, where word lines WL1 and WL2 may be the same as word lines RWL1 and RWL2, respectively.
U.S. Pat. No. 6,055,178 (Naji) is directed to an MRAM device comprising a memory array and a reference memory array, wherein the reference memory array is formed from magnetic memory cells to hold reference data in a row line. In U.S. Pat. No. 6,317,376 B1 and U.S. Pat. No. 6,385,111 B2 (Tran et al.) an MRAM device is directed to generating reference signals that are used to determine the resistance states of each memory cell. U.S. Pat. No. 6,426,907 B1 (Hoenigschmid) is directed to a reference circuit for an MRAM array, wherein reference cells representing a logical “1” and reference cells representing a logical “0” are coupled in parallel to establish a reference to measure the logical state of the memory cells. U.S. Pat. No. 6,697,294 B1 (Qi et al.) is directed a reference circuit for a magnetic tunnel junction MRAM, including two magnetic tunnel junctions, wherein one of the two is set to a low state and the second to a high state. In U.S. Pat. No. 6,870,760 B2 (Tsang) a method and system is directed to reading a magnetic memory, wherein a second state of a memory cell is determined using a disturb magnetic field thereby negating the need of a separate reference element. U.S. Pat. No. 7,321,507 B2 and U.S. Pat. No. 7,499,314 B2 (Yang et al) are directed to an MRAM reference cell sub-array that provides a mid point reference current to sense amplifiers. U.S. Pat. No. 7,613,868 B2 (Yang et al.) is directed to a system and method for reading and programming a magnetic memory cells. In U.S. Pat. No. 7,800,937 B2 (Hung et al.) a method is directed to reading an MRAM device, which includes partially switching magnetic moments in a reference cell to generate a reference current to be compared to a read current of a memory cell. U.S. Pat. No. 7,885,131 B2 (Sakimura et al.) is directed to a magnetic memory device, wherein a memory cell and a reference cell store data based on change in resistance value. US2002/0080648 A1 (Kim) is directed to a circuit for sensing a memory cell, which includes a memory cell and a reference cell.
When reading an MRAM using reference devices to create a reference current for comparison, the read margin is defined as the signal separation between that of the memory cells and the reference cells. There are three major sources of variations in reading an MRAM. The first is the sense-amp to sense amp variations, usually manifesting itself as variation of sense amp offset, which can be overcome by adjusting offset of each sense amp at factory. The second source of variation is the contribution from parasitic impendence, e.g. bit line resistance. This is often overcome by mimicking memory device bit lines with reference bit lines, and select from the multitude of reference devices ones that have similar parasitic impedance and loading as the target devices. The third source of variations is from the variations between reference devices. This can be minimized by averaging more reference devices. The usual minimum of two reference bit lines already reduces this variation by a factor of 1.4. Some system averages four reference bit lines to get a 2× reduction. Some architecture allows the averaging of even more reference devices to further reduce this. Because the variation of the two signal levels of “0” and “1” is not the same, the optimal reference level is not necessarily midway between “0” and “1” signal levels. So a systematic offset of the reference signal may be desired to bring it either closer to “0” or to “1”.
The aforementioned methodologies are directed to producing an optimal consistent reference signal relative to the memory cell signals, but as devices are scaled smaller, both the manufacturing process and the material uniformity induces more device to device variations. When the variation reach a certain level, even a “perfect” reference signal is no longer adequate to allow reliably reading operations. To illustrate this issue FIG. 2 plots the resistance distribution Rp 20 and Rap 21 of the two magnetic states assuming a resistance covariance of 5% and a magneto-resistance ((Rap−Rp)/Rp) of 80% with a covariance of 5%. For a memory block of 8 Mb, it is clear from this graph that the strategy of using one consistent reference signal level is simply not a solution.
In FIG. 2 it is shown that the two distributions of Rp and Rap overlap so that the two levels cannot be distinguished for all the 8 Mbits based on a resistance/current measurement. Typical covariance of the junction resistance for an magnetic tunnel junction (MTJ) array is 3.5% to 8% with a tunnel magneto-resistance (TMR) ratio of about 70% to 130%.